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Optimization for SEU/SET immunity on 0.15 $$mu$$m fully depleted CMOS/SOI digital logic devices

Makihara, Akiko*; Asai, Hiroaki*; Tsuchiya, Yoshihisa*; Amano, Yukio*; Midorikawa, Masahiko*; Shindo, Hiroyuki*; Kuboyama, Satoshi*; Onoda, Shinobu; Hirao, Toshio; Nakajima, Yasuhito*; Takahashi, Yoshihiro*; Onishi, Kazunori*

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