Interface engineering of ZrO/Ge gate stacks by post-deposition annealing and AlO capping layers

成膜後の加熱とAlOキャップ層によるZrO/Geゲートスタックの界面工学

渡部 平司*; 岡本 学*; 朽木 克博*; Harries, J.; 吉越 章隆 ; 寺岡 有殿; 細井 卓治*; 志村 考功*

Watanabe, Heiji*; Okamoto, Gaku*; Kutsuki, Katsuhiro*; Harries, J.; Yoshigoe, Akitaka; Teraoka, Yuden; Hosoi, Takuji*; Shimura, Takayoshi*

High-k絶縁膜としてZrO膜をGe基板上に堆積した後に熱酸化処理を施すことでGe-MOSの界面設計を検討した。放射光XPS分析の結果、酸化初期では界面でミキシングが起こり、その後にGeO層が成長することを確認した。一方、AlO/ZrO/Ge構造では、AlO膜の低い酸素透過性により熱酸化時の界面酸化反応が抑制され、EOTの薄層化に有効であることを確認した。

We fabricated high-quality high-k/Ge gate stacks by direct deposition of ZrO layers on Ge substrates and subsequent post-deposition annealing. Synchrotron-radiation X-ray photoelectron spectroscopy revealed that thermally oxidizing a ZrO/Ge structure at 823 K caused not only ZrO and Ge to intermix but also a pure GeO interlayer to form. By optimizing subsequent oxidation conditions, we obtained a minimum EOT of 1.9 nm, negligible C-V hysteresis, and an interface state density (Dit) of a few 10 cmeV for Au/ZrO/Ge capacitors. We also developed AlO/ZrO stacked gate dielectrics to control interface reaction during the post treatment. The AlO capping on the ZrO layer was found to be beneficial for further EOT scaling because it suppressed excess interface reaction. Scaled EOT value down to 1.6 nm and leakage current reduction were achieved.