High-k/Ge gate stack with an EOT of 0.56 nm by controlling interface reaction using ultrathin AlO interlayer

極薄AlOを中間層に用いた界面反応制御による0.56nmのEOTを持つ高誘電率薄膜/Geゲートスタック

細井 卓治*; 秀島 伊織*; 田中 亮平*; 箕浦 佑也*; 吉越 章隆 ; 寺岡 有殿; 志村 考功*; 渡部 平司*

Hosoi, Takuji*; Hideshima, Iori*; Tanaka, Ryohei*; Minoura, Yuya*; Yoshigoe, Akitaka; Teraoka, Yuden; Shimura, Takayoshi*; Watanabe, Heiji*

Metal/high-k gate stacks on Ge channel with less than 0.7 nm EOT must be developed to realize 15-nm-node CMOS devices. Recently, a Ge-MOSFET operation with 0.7 nm EOT has been demonstrated using a HfO/AlO/GeO/Ge gate stack formed by plasma oxidation through the HfO/AlO stack. The plasma oxidation of HfO/Ge resulted in the relatively degraded insulating and interface properties. This suggests that underlying AlO layer is beneficial in improving the high-k and GeO interlayers. However, the role of AlO layer in HfO/AlO/GeO/Ge stack is not well understood. We systematically investigated an effect of AlO interlayer on EOT scaling focusing on the Ge diffusion into the HfO layer by synchrotron radiation photoemission spectroscopy and electrical characterization. We achieved 0.56 nm EOT with 5 orders of magnitude lower leakage current compared to the poly-Si/Si stack.