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Hoshino, Eijiro*; Kobayashi, Daisuke*; Makino, Takahiro; Oshima, Takeshi; Hirose, Kazuyuki*
Proceedings of 10th International Workshop on Radiation Effects on Semiconductor Devices for Space Applications (RASEDA-10) (Internet), p.130 - 133, 2012/12
Single event effects on phase locked loops (PLLs) are experimentally investigated. Test chips of the PLLs are fabricated in a 0.2-
m fully-depleted silicon-on-insulator technology. The PLL architecture is designed in conjunction with hardening techniques such as the triple modular redundancy and a stacked transistor design approach. A heavy-ion beam test confirms that the hardened PLL exhibits higher radiation tolerance than non-hardened one for 7.5-MeV Ne irradiation: The accelerated ions have the linear energy transfer of 7.3 MeV/cm
/mg in Si.
Hoshino, Eijiro*; Kobayashi, Daisuke*; Hirose, Kazuyuki*; Makino, Takahiro; Oshima, Takeshi
no journal, ,
no abstracts in English
m FD-SOI processHoshino, Eijiro*; Shibata, Yuichi*; Kobayashi, Daisuke*; Kakehashi, Yuya*; Makino, Takahiro; Oshima, Takeshi; Hirose, Kazuyuki*
no journal, ,
no abstracts in English
Kobayashi, Daisuke*; Hoshino, Eijiro*; Shibata, Yuichi*; Kakehashi, Yuya*; Hirose, Kazuyuki*; Makino, Takahiro; Oshima, Takeshi
no journal, ,
no abstracts in English