Electrical properties and energy band alignment of SiO/GaN metal-oxide-semiconductor structures fabricated on N-polar GaN(000) substrates

Mizobata, Hidetoshi*; Tomigahara, Kazuki*; Nozaki, Mikito*; Kobayashi, Takuma*; Yoshigoe, Akitaka; Hosoi, Takuji*; Shimura, Takayoshi*; Watanabe, Heiji*

Applied Physics Letters, 121(6), p.062104_1 - 062104_6, 2022/08

https://doi.org/10.1063/5.0095468

The interface properties and energy band alignment of SiO/GaN metal-oxide-semiconductor (MOS) structures fabricated on N-polar GaN(000) substrates were investigated by electrical measurements and synchrotron-radiation X-ray photoelectron spectroscopy. They were then compared with those of SiO/GaN MOS structures on Ga-polar GaN(0001). Although the SiO/GaN(000) structure was found to be more thermally unstable than that on the GaN(0001) substrate, excellent electrical properties were obtained for the SiO/GaN(000) structure by optimizing conditions for post-deposition annealing. However, the conduction band offset for SiO/GaN(000) was smaller than that for SiO/GaN(0001), leading to increased gate leakage current. Therefore, caution is needed when using N-polar GaN(000) substrates for MOS device fabrication.

Comprehensive physical and electrical characterizations of NO nitrided SiO/4H-SiC(110) interfaces

Nakanuma, Takato*; Iwakata, Yu*; Watanabe, Arisa*; Hosoi, Takuji*; Kobayashi, Takuma*; Sometani, Mitsuru*; Okamoto, Mitsuo*; Yoshigoe, Akitaka; Shimura, Takayoshi*; Watanabe, Heiji*

Japanese Journal of Applied Physics, 61(SC), p.SC1065_1 - SC1065_8, 2022/05

https://doi.org/10.35848/1347-4065/ac4685

Nitridation of SiO/4H-SiC(110) interfaces with post-oxidation annealing in an NO ambient (NO-POA) and its impact on the electrical properties were investigated. Sub-nm-resolution nitrogen depth profiling at the interfaces was conducted by using a scanning X-ray photoelectron spectroscopy microprobe. The results showed that nitrogen atoms were incorporated just at the interface and that interface nitridation proceeded much faster than at SiO/SiC(0001) interfaces, resulting in a 2.3 times higher nitrogen concentration. Electrical characterizations of metal-oxide-semiconductor capacitors were conducted through capacitance-voltage () measurements in the dark and under illumination with ultraviolet light to evaluate the electrical defects near the conduction and valence band edges and those causing hysteresis and shifting of the curves. While all of these defects were passivated with the progress of the interface nitridation, excessive nitridation resulted in degradation of the MOS capacitors. The optimal conditions for NO-POA are discussed on the basis of these experimental findings.

Evaluation and mitigation of reactive ion etching-induced damage in AlGaN/GaN MOS structures fabricated by low-power inductively coupled plasma

Nozaki, Mikito*; Terashima, Daiki*; Yoshigoe, Akitaka; Hosoi, Takuji*; Shimura, Takayoshi*; Watanabe, Heiji*

Japanese Journal of Applied Physics, 59(SM), p.SMMA07_1 - SMMA07_7, 2020/07

https://doi.org/10.35848/1347-4065/ab8f0e

AlGaN/GaN metal-oxide-semiconductor (MOS) structures were fabricated by low-power inductively coupled plasma reactive ion etching and chemical vapor deposition of SiO dielectrics on the etched surfaces, and they were systematically investigated by physical and electrical characterizations in an effort to develop a low-damage recessed gate process. The comprehensive research demonstrates the significant advantages of the proposed low-damage recessed gate process for fabricating next-generation AlGaN/GaN MOS-HFET devices.

SiO/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

Watanabe, Kenta*; Terashima, Daiki*; Nozaki, Mikito*; Yamada, Takahiro*; Nakazawa, Satoshi*; Ishida, Masahiro*; Anda, Yoshiharu*; Ueda, Tetsuzo*; Yoshigoe, Akitaka; Hosoi, Takuji*; et al.

Japanese Journal of Applied Physics, 57(6S3), p.06KA03_1 - 06KA03_6, 2018/06

https://doi.org/10.7567/JJAP.57.06KA03

The advantage of SiO/AlON stacked gate dielectrics over SiO, AlON and AlO single dielectric layers was demonstrated. Our systematic research revealed that the optimized stacked structure with 3.3-nm-thick AlON interlayer is beneficial in terms of superior interface quality, reduced gate leakage current and C-V hysteresis for next-generation high frequency and high power AlGaN/GaN MOS-HFETs.

Control of Ga-oxide interlayer growth and Ga diffusion in SiO/GaN stacks for high-quality GaN-based metal-oxide-semiconductor devices with improved gate dielectric reliability

Yamada, Takahiro*; Watanabe, Kenta*; Nozaki, Mikito*; Yamada, Hisashi*; Takahashi, Tokio*; Shimizu, Mitsuaki*; Yoshigoe, Akitaka; Hosoi, Takuji*; Shimura, Takayoshi*; Watanabe, Heiji*

Applied Physics Express, 11(1), p.015701_1 - 015701_4, 2018/01

https://doi.org/10.7567/APEX.11.015701

A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal-oxide-semiconductor (MOS) devices was developed on the basis of systematic physical and electrical characterizations. Chemical vapor deposition of SiO films directly onto GaN substrates forming Ga-oxide interlayers was used to fabricate SiO/GaO/GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state density below 10cmeV were obtained by post-deposition annealing, Ga diffusion into overlying SiO layers severely degraded the insulating property and dielectric breakdown characteristics of the MOS devices. However, this problem was found to be solved by employing rapid thermal processing, leading to superior performance of the GaN-MOS devices in terms of interface quality, insulating property and gate dielectric reliability.

Comprehensive study on initial thermal oxidation of GaN(0001) surface and subsequent oxide growth in dry oxygen ambient

Yamada, Takahiro*; Ito, Joyo*; Asahara, Ryohei*; Watanabe, Kenta*; Nozaki, Mikito*; Nakazawa, Satoshi*; Anda, Yoshiharu*; Ishida, Masahiro*; Ueda, Tetsuzo*; Yoshigoe, Akitaka; et al.

Journal of Applied Physics, 121(3), p.035303_1 - 035303_9, 2017/01

https://doi.org/10.1063/1.4974458

Initial oxidation of GaN(0001) epilayers and subsequent growth of thermal oxides in dry oxygen ambient were investigated by means of X-ray photoelectron spectroscopy, spectroscopic ellipsometry, atomic force microscopy and X-ray diffraction measurements. It was found that, whereas initial oxide formation tends to saturate at temperatures below 800C, selective growth of small oxide grains proceeds at dislocations in the epilayers, followed by noticeable grain growth leading to rough surface morphology at higher oxidation temperatures. This indicates that oxide growth and its morphology are crucially dependent on the defect density in the GaN epilayers. Structural characterizations also revealed that polycrystalline - and -phase GaO grains in an epitaxial relation with the GaN substrate are formed from the initial stage of the oxide growth. On the basis of these experimental findings, we also developed a comprehensive model for GaN oxidation mediated by nitrogen removal and mass transport.

Synchrotron radiation X-ray photoelectron spectroscopy of Ti/Al ohmic contacts to n-type GaN; Key role of Al capping layers in interface scavenging reactions

Nozaki, Mikito*; Ito, Joyo*; Asahara, Ryohei*; Nakazawa, Satoshi*; Ishida, Masahiro*; Ueda, Tetsuzo*; Yoshigoe, Akitaka; Hosoi, Takuji*; Shimura, Takayoshi*; Watanabe, Heiji*

Applied Physics Express, 9(10), p.105801_1 - 105801_4, 2016/10

https://doi.org/10.7567/APEX.9.105801

Interface reactions between Ti-based electrodes and n-type GaN epilayers were investigated by synchrotron radiation X-ray photoelectron spectroscopy. Metallic Ga and thin TiN alloys were formed at the interface by subsequently depositing Al capping layers on ultrathin Ti layers even at room temperature. By comparing results from stacked Ti/Al and single Ti electrodes, the essential role of Al capping layers serving as an oxygen-scavenging element to produce reactive Ti underlayers was demonstrated. Further growth of the metallic interlayer during annealing was observed. A strategy for achieving low-resistance ohmic contacts to n-GaN with low-thermal-budget processing is discussed.

High-/Ge gate stack with an extremely thin-EOT by controlling interface reaction using ultrathin AlO interlayer

Tanaka, Ryohei*; Hideshima, Iori*; Minoura, Yuya*; Yoshigoe, Akitaka; Teraoka, Yuden; Hosoi, Takuji*; Shimura, Takayoshi*; Watanabe, Heiji*

Dai-19-Kai Getosutakku KenkyuKai Yokoshu, p.5 - 8, 2014/01

Germanide formation in metal/high-/Ge gate stacks and its impact on electrical properties

Hosoi, Takuji*; Hideshima, Iori*; Minoura, Yuya*; Tanaka, Ryohei*; Yoshigoe, Akitaka; Teraoka, Yuden; Shimura, Takayoshi*; Watanabe, Heiji*

Shingaku Giho, 113(87), p.19 - 23, 2013/06

An understanding of the mechanisms responsible for formation or decomposition of GeO interlayer and Ge diffusion into high- layer is important to develop advanced metal/high- gate stacks for Ge MOSFETs. In this work, we fabricated HfO/GeO/Ge gate stacks by oxidation of thin metal Hf layers on Ge substrates. The effect of plasma oxidation on the change in the bonding states of Ge atoms in HfO/GeO/Ge gate stacks and the structural changes induced by metal electrode deposition and thermal annealing was systematically investigated by synchrotron radiation photoemission spectroscopy (SR-PES) and electrical characterization.

Impact of interface defect passivation on conduction band offset at SiO/4H-SiC interface

Hosoi, Takuji*; Kirino, Takashi*; Chanthaphan, A.*; Uenishi, Yusuke*; Ikeguchi, Daisuke*; Yoshigoe, Akitaka; Teraoka, Yuden; Mitani, Shuhei*; Nakano, Yuki*; Nakamura, Takashi*; et al.

Materials Science Forum, 717-720, p.721 - 724, 2012/05

https://doi.org/10.4028/www.scientific.net/MSF.717-720.721