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Abe, Shinichiro; Sato, Tatsuhiko; Kuroda, Junya*; Manabe, Seiya*; Watanabe, Yukinobu*; Liao, W.*; Ito, Kojiro*; Hashimoto, Masanori*; Harada, Masahide; Oikawa, Kenichi; et al.
Proceedings of IEEE International Reliability Physics Symposium (IRPS 2020) (Internet), 6 Pages, 2020/04
Single event upsets (SEUs) caused by neutrons have been recognized as a serious reliability problem for microelectronic devices on the ground level. In our previous work, it was found that hydride placed in front of the memory chip has considerably impact on SEU cross sections because H ions generated via elastic scattering of neutrons with hydrogen atoms are only emitted in a forward direction. In this study, the effect of components neighboring transistors on neutron-induced SEUs was investigated for 65-nm bulk SRAMs by using PHITS. It was found that the shape of the SEU cross section around few MeV comes from the thickness and the position of components placed in front of transistors when that components do not contains hydrogen atoms. By considering components adjoin memory cells in the test board used in the simulation, measured data at J-PARC BL10 were reproduced well. In addition, it was found that the effect of components neighboring transistors on neutron-induced SERs does not negligible in terrestrial environment.
Abe, Shinichiro; Liao, W.*; Manabe, Seiya*; Sato, Tatsuhiko; Hashimoto, Masanori*; Watanabe, Yukinobu*
IEEE Transactions on Nuclear Science, 66(7, Part2), p.1374 - 1380, 2019/07
Times Cited Count：3 Percentile：57.07(Engineering, Electrical & Electronic)Single event upsets (SEUs) caused by secondary cosmic-ray neutrons have recognized as a serious reliability problem for microelectronic devices. Acceleration tests at neutron facilities are convenient to validate soft error rates (SERs) quickly, but some corrections caused from measurement conditions are required to derive realistic SERs at actual environment or to compare other measured data. In this study, the effect of irradiation side on neutron-induced SEU cross sections was investigated by performing neutron transport simulation using PHITS. SERs for 65-nm bulk CMOS SRAMs are estimated using the sensitive volume model. It was found from simulation that SERs for the sealant side irradiation are 30-50% larger than those for the board side irradiation. This difference comes from the difference of production yield and angular distribution of secondary H and He ions, which are the main cause of SEUs. Thus the direction of neutron irradiation should be reported when the result of acceleration tests are published. This result also indicates that SERs can be reduced by equipping device with sealant side facing downward.
Manabe, Seiya*; Watanabe, Yukinobu*; Liao, W.*; Hashimoto, Masanori*; Nakano, Keita*; Sato, Hikaru*; Kin, Tadahiro*; Abe, Shinichiro; Hamada, Koji*; Tampo, Motonobu*; et al.
IEEE Transactions on Nuclear Science, 65(8), p.1742 - 1749, 2018/08
Times Cited Count：6 Percentile：64.98(Engineering, Electrical & Electronic)Recently, the malfunction of microelectronics caused by secondary cosmic-ray muon is concerned as semiconductor devices become sensitive to radiation. In this study, we have performed muon irradiation testing for 65-nm ultra-thin body and thin buried oxide (UTBB-SOI) SRAMs in the Japan Proton Accelerator Research Complex (J-PARC), in order to investigate dependencies of single event upset (SEU) cross section on incident muon momentum and supply voltage. It was found that the SEU cross section by negative muon are approximately two to four times larger than those by positive muon in the momentum range from 35 MeV/c to 39 MeV/c. The supply voltage dependence of muon-induced SEU cross section was measured with the momentum of 38 MeV/c. SEU cross sections decrease with increasing supply voltage, but the decreasing of SEU cross section by negative muon is gentler than that by positive muon. Experimental data of positive and negative muon irradiation with the momentum of 38 MeV/c were analyzed by PHITS. It was clarified that the negative muon capture causes the difference between the SEU cross section by negative muon and that by positive muon.
Liao, W.*; Hashimoto, Masanori*; Manabe, Seiya*; Watanabe, Yukinobu*; Abe, Shinichiro; Nakano, Keita*; Sato, Hikaru*; Kin, Tadahiro*; Hamada, Koji*; Tampo, Motonobu*; et al.
IEEE Transactions on Nuclear Science, 65(8), p.1734 - 1741, 2018/08
Times Cited Count：12 Percentile：91.11(Engineering, Electrical & Electronic)Soft error induced by secondary cosmic-ray muon is concerned since susceptibility of semiconductor device to soft error increases with the scaling of technology. In this study, we have performed irradiation tests of muons on 65-nm bulk CMOS SRAM in the Japan Proton Accelerator Research Complex (J-PARC) and measured soft error rate (SER) to investigate mechanism of muon-induced soft errors. It was found that SER by negative muon increases above 0.5 V supply voltage, although SER by positive muon increases monotonically as the supply voltage lowers. SER by negative muon also increases with forward body bias. In addition, negative muon causes large multiple cell upset (MCU) of more than 20 bits and the ratio of MCU events to all the events is 66% at 1.2V supply voltage. These tendencies indicate that parasitic bipolar action (PBA) is highly possible to contribute to SER by negative muon. Experimental data are analyzed by PHITS. It was found that negative muon can deposit larger charge than positive muon, and such events that can deposit large charge may trigger PBA.
