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Onishi, Kentaro*; Kobayashi, Takuma*; Mizobata, Hidetoshi*; Nozaki, Mikito*; Yoshigoe, Akitaka; Shimura, Takayoshi*; Watanabe, Heiji*
Japanese Journal of Applied Physics, 62(5), p.050903_1 - 050903_4, 2023/05
While the formation of an GaO interlayer is key to achieving SiO/GaN interfaces with low defect density, it can affect the reliability and stability of metal-oxide-semiconductor (MOS) devices if the annealing conditions are not properly designed. In the present study, we aimed to minimize the growth of the GaO layer on the basis of the sputter deposition of SiO on GaN. Synchrotron radiation X-ray photoelectron spectrometry measurements confirmed the suppressed growth of the GaO layer compared with a SiO/GaN structure formed by plasma-enhanced chemical vapor deposition. Negligible GaO growth was also observed when subsequent oxygen annealing up to 600C was performed. A MOS device with negligible capacitance-voltage hysteresis, nearly ideal flat-band voltage, and low leakage current was demonstrated by performing oxygen and forming gas annealing at temperatures of 600C and 400C, respectively.
Mizobata, Hidetoshi*; Tomigahara, Kazuki*; Nozaki, Mikito*; Kobayashi, Takuma*; Yoshigoe, Akitaka; Hosoi, Takuji*; Shimura, Takayoshi*; Watanabe, Heiji*
Applied Physics Letters, 121(6), p.062104_1 - 062104_6, 2022/08
Times Cited Count:1 Percentile:17.38(Physics, Applied)The interface properties and energy band alignment of SiO/GaN metal-oxide-semiconductor (MOS) structures fabricated on N-polar GaN(000) substrates were investigated by electrical measurements and synchrotron-radiation X-ray photoelectron spectroscopy. They were then compared with those of SiO/GaN MOS structures on Ga-polar GaN(0001). Although the SiO/GaN(000) structure was found to be more thermally unstable than that on the GaN(0001) substrate, excellent electrical properties were obtained for the SiO/GaN(000) structure by optimizing conditions for post-deposition annealing. However, the conduction band offset for SiO/GaN(000) was smaller than that for SiO/GaN(0001), leading to increased gate leakage current. Therefore, caution is needed when using N-polar GaN(000) substrates for MOS device fabrication.
Onishi, Kentaro*; Kobayashi, Takuma*; Mizobata, Hidetoshi*; Nozaki, Mikito*; Yoshigoe, Akitaka; Shimura, Takayoshi*; Watanabe, Heiji*
no journal, ,
GaO interlayer at SiO/GaN interfaces is easily reduced during the annealing process, leading to threshold voltage instability of MOS devices. In this study, we formed SiO by sputter deposition to minimize the growth of unstable GaO interlayer. Furthermore, by performing oxygen and hydrogen annealing, a stable GaN MOS structure with good interface and insulating properties was realized.