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Journal Articles

Gate stack technologies for silicon carbide power MOS devices

Hosoi, Takuji*; Kirino, Takashi*; Uenishi, Yusuke*; Ikeguchi, Daisuke*; Chanthaphan, A.*; Yoshigoe, Akitaka; Teraoka, Yuden; Mitani, Shuhei*; Nakano, Yuki*; Nakamura, Takashi*; et al.

Workshop digest of 2012 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD 2012), p.22 - 25, 2012/06

Journal Articles

Synchrotron radiation photoelectron spectroscopy study of thermally grown oxides on 4H-SiC(0001) Si-face and (000-1) C-face substrates

Watanabe, Heiji*; Hosoi, Takuji*; Kirino, Takashi*; Uenishi, Yusuke*; Chanthaphan, A.*; Yoshigoe, Akitaka; Teraoka, Yuden; Mitani, Shuhei*; Nakano, Yuki*; Nakamura, Takashi*; et al.

Materials Science Forum, 717-720, p.697 - 702, 2012/05

 Times Cited Count:2 Percentile:79.2

Journal Articles

Impact of interface defect passivation on conduction band offset at SiO$$_{2}$$/4H-SiC interface

Hosoi, Takuji*; Kirino, Takashi*; Chanthaphan, A.*; Uenishi, Yusuke*; Ikeguchi, Daisuke*; Yoshigoe, Akitaka; Teraoka, Yuden; Mitani, Shuhei*; Nakano, Yuki*; Nakamura, Takashi*; et al.

Materials Science Forum, 717-720, p.721 - 724, 2012/05

 Times Cited Count:4 Percentile:91.47

Journal Articles

Synchrotron X-ray photoelectron spectroscopy study on thermally grown SiO$$_{2}$$/4H-SiC(0001) interface and its correlation with electrical properties

Watanabe, Heiji*; Hosoi, Takuji*; Kirino, Takashi*; Kagei, Yusuke*; Uenishi, Yusuke*; Chanthaphan, A.*; Yoshigoe, Akitaka; Teraoka, Yuden; Shimura, Takayoshi*

Applied Physics Letters, 99(2), p.021907_1 - 021907_3, 2011/07

 Times Cited Count:104 Percentile:95.84(Physics, Applied)

Journal Articles

Impact of stacked AlON/SiO$$_{2}$$ gate dielectrics for SiC power devices

Watanabe, Heiji*; Kirino, Takashi*; Uenishi, Yusuke*; Chanthaphan, A.*; Yoshigoe, Akitaka; Teraoka, Yuden; Mitani, Shuhei*; Nakano, Yuki*; Nakamura, Takashi*; Hosoi, Takuji*; et al.

ECS Transactions, 35(2), p.265 - 274, 2011/05

 Times Cited Count:7 Percentile:93.25

Journal Articles

Gate stack technologies for SiC power MOSFETs

Watanabe, Heiji*; Hosoi, Takuji*; Kirino, Takashi*; Uenishi, Yusuke*; Chanthaphan, A.*; Ikeguchi, Daisuke*; Yoshigoe, Akitaka; Teraoka, Yuden; Mitani, Shuhei*; Nakano, Yuki*; et al.

ECS Transactions, 41(3), p.77 - 90, 2011/00

 Times Cited Count:3 Percentile:85.69

Oral presentation

Impact of Ge$$_{3}$$N$$_{4}$$ interface layer on EOT scaling in high-k/Ge gate stacks

Kutsuki, Katsuhiro*; Okamoto, Gaku*; Hideshima, Iori*; Uenishi, Yusuke*; Kirino, Takashi*; Harries, J.; Yoshigoe, Akitaka; Teraoka, Yuden; Hosoi, Takuji*; Shimura, Takayoshi*; et al.

no journal, , 

Direct deposition of ZrO$$_{2}$$ films on Ge substrates and subsequent thermal oxidation results in an equivalent oxide thickness (EOT) of above 2 nm while obtaining good interface quality due to interfacial GeO$$_{2}$$ formation. In this work, we proposed the use of Ge$$_{3}$$N$$_{4}$$ interlayer formed by high-density plasma nitridation for further EOT scaling because of its high resistance to oxidation and superior thermal stability. The structural modification of ZrO$$_{2}$$/Ge$$_{3}$$N$$_{4}$$/Ge after oxidation was characterized by synchrotron-radiation X-ray photoelectron spectroscopy at BL23SU in SPring-8. Ge 3d core-level spectra revealed that the Ge$$_{3}$$N$$_{4}$$ interlayer was slightly oxidized after thermal oxidation at 823 K, but N 1s spectra remained almost unchanged. This indicates that the Ge$$_{3}$$N$$_{4}$$ interlayer is effective in suppressing interfacial oxidation, thus obtaining an EOT of 1.8 nm.

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