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Journal Articles

EPR and pulsed ENDOR study of EI6 and related defects in 4$$H$$-SiC

Umeda, Takahide*; Ishitsuka, Yuya*; Isoya, Junichi*; Morishita, Norio; Oshima, Takeshi; Kamiya, Tomihiro

Materials Science Forum, 457-460, p.465 - 468, 2004/10

EPR/pulsed-ENDOR study of silicon antisite defects in p- and n-type 4$$H$$-SiC, which were generated by high-temperature (800 $$^{circ}$$C) electron irradiation. For this type of defects, only a positively-charged state (Si$$_{C}$$$$^{+}$$) in p-type 4$$H$$-SiC has been observed so far; however, we found a new signal in n-type 4$$H$$-SiC, which was most likely to be assigned to a negatively-charged silicon antisite (Si$$_{C}$$$$^{-}$$). Both silicon antisite signals in p- and n-type samples showed a large variation in $$^{29}$$Si hyperfine (HF) interactions with decreasing the temperature. This indicates the presence of a large structural relaxation surrounding the defect.

Journal Articles

Comparison of the electrical channel properties between dry- and wet-oxidized 6H-SiC MOSFETs investigated by Hall effect

Laube, M.*; Pensl, G.*; Lee, K. K.; Oshima, Takeshi

Materials Science Forum, 457-460, p.1381 - 1384, 2004/10

The electrical properties of n-channel 6H-SiC MOSFETs have been studied by temperature-dependent current-voltage and Hall effect measurements. The MOS transistors are either wet (sample A) or dry oxidized followed by a post-annealing step at 1100$$^{circ}$$C and a pyrogenic reoxidation at 800$$^{circ}$$C (sample B). Higher drain transconductance and saturation currents are observed in sample B. The Hall effect investigations show that this improvement in the performance of the MOS transistors (sample B) is caused by a lower degree of trapping of free electrons. The density of interface traps D$$_{IT}$$ close to the conduction band edge has been determined from the shift of the threshold voltage V$$_{TH}$$ as a function of the temperature and from the Hall effect results. D$$_{IT}$$ is about two times lower in sample B. The room temperature value of the electron Hall mobility is determined to be about 60 cm$$^{2}$$/Vs for both samples; it increases with decreasing temperature.

Journal Articles

Investigation of SiO$$_2$$/SiC interface using positron annihilation technique

Maekawa, Masaki; Kawasuso, Atsuo; Yoshikawa, Masahito; Ichimiya, Ayahiko

Materials Science Forum, 457-460(Part2), p.1301 - 1304, 2004/06

no abstracts in English

Journal Articles

Relationship between the current direction in the inversion layer and the electrical characteristics of metal-oxide-semiconductor field effect transistors on 3C-SiC

Oshima, Takeshi; Lee, K. K.; Ishida, Yuki*; Kojima, Kazutoshi*; Tanaka, Yasunori*; Takahashi, Tetsuo*; Yoshikawa, Masahito; Okumura, Hajime*; Arai, Kazuo*; Kamiya, Tomihiro

Materials Science Forum, 457-460(Part2), p.1405 - 1408, 2004/06

The electrical characteristics of cubic silicon carbide (3C-SiC) Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with the current direction in the inversion layer perpendicular to [-110] ([-110]-perpendicular MOSFETs) were compared to those of 3C-SiC MOSFETs with the current direction in the inversion layer parallel to [-110] ([-110]-parallel MOSFETs). The threshold voltage (V$$_{T}$$) for both MOSFETs shows -0.5 V although enhancement type MOSFETs were designed. The values of channel mobility which was estimated from linear region of drain current (I$$_{D}$$) - drain voltage (V$$_{D}$$) curves are 230 cm$$^{2}$$/Vs for [-110]-perpendicular MOSFETs and 215 cm$$^{2}$$/Vs for [-110]-parallel MOSFETs, indicating no significant difference between both MOSFETs. The value of I$$_{D}$$ for [-110]-perpendicular MOSFETs is of order of 10-8 A at V$$_{D}$$ = 10V and gate voltage (V$$_{G}$$) of -2V. However, for [-110]-parallel MOSFETs, I$$_{D}$$ shows of order of -10-6 A at V$$_{D}$$ = 10V and V$$_{G}$$ = -2V.

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