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Makino, Takahiro; Kobayashi, Daisuke*; Hirose, Kazuyuki*; Takahashi, Daisuke*; Ishii, Shigeru*; Kusano, Masaki*; Onoda, Shinobu; Hirao, Toshio; Oshima, Takeshi
IEEE Transactions on Nuclear Science, 56(6), p.3180 - 3184, 2009/12
Times Cited Count：13 Percentile：64.65(Engineering, Electrical & Electronic)SET-induced soft-error rates (
s) of logic LSIs are estimated from SET pulse-widths measured in logic cells used in logic LSIs. The estimated rates are consistent with directly measured s for logic LSIs.
Makino, Takahiro*; Kobayashi, Daisuke*; Hirose, Kazuyuki*; Yanagawa, Yoshimitsu*; Saito, Hirobumi*; Ikeda, Hirokazu*; Takahashi, Daisuke*; Ishii, Shigeru*; Kusano, Masaki*; Onoda, Shinobu; et al.
IEEE Transactions on Nuclear Science, 56(1), p.202 - 207, 2009/02
Times Cited Count：36 Percentile：90.61(Engineering, Electrical & Electronic)SET pulse-widths were measured as a function of LET by using pulse capture circuits and were simulated with mixed-mode 3-D device simulations. We found that the carrier recombination process dominates LET dependence of SET pulse-widths.
Makino, Takahiro*; Yanagawa, Yoshimitsu*; Kobayashi, Daisuke*; Fukuda, Seisuke*; Hirose, Kazuyuki*; Ikeda, Hirokazu*; Saito, Hirobumi*; Onoda, Shinobu; Hirao, Toshio; Oshima, Takeshi; et al.
Shingaku Giho, 108(100), p.67 - 72, 2008/06
SET pulse-widths were measured as a function of LET by using pulse capture circuits. In addition, a scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI system.
Makino, Takahiro*; Kobayashi, Daisuke*; Hirose, Kazuyuki*; Yanagawa, Yoshimitsu*; Saito, Hirobumi*; Ikeda, Hirokazu*; Takahashi, Daisuke*; Ishii, Shigeru*; Kusano, Masaki*; Onoda, Shinobu; et al.
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