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Journal Articles

Evaluation and mitigation of reactive ion etching-induced damage in AlGaN/GaN MOS structures fabricated by low-power inductively coupled plasma

Nozaki, Mikito*; Terashima, Daiki*; Yoshigoe, Akitaka; Hosoi, Takuji*; Shimura, Takayoshi*; Watanabe, Heiji*

Japanese Journal of Applied Physics, 59(SM), p.SMMA07_1 - SMMA07_7, 2020/07

 Times Cited Count:2 Percentile:12.5(Physics, Applied)

AlGaN/GaN metal-oxide-semiconductor (MOS) structures were fabricated by low-power inductively coupled plasma reactive ion etching and chemical vapor deposition of SiO$$_{2}$$ dielectrics on the etched surfaces, and they were systematically investigated by physical and electrical characterizations in an effort to develop a low-damage recessed gate process. The comprehensive research demonstrates the significant advantages of the proposed low-damage recessed gate process for fabricating next-generation AlGaN/GaN MOS-HFET devices.

Journal Articles

SiO$$_{2}$$/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

Watanabe, Kenta*; Terashima, Daiki*; Nozaki, Mikito*; Yamada, Takahiro*; Nakazawa, Satoshi*; Ishida, Masahiro*; Anda, Yoshiharu*; Ueda, Tetsuzo*; Yoshigoe, Akitaka; Hosoi, Takuji*; et al.

Japanese Journal of Applied Physics, 57(6S3), p.06KA03_1 - 06KA03_6, 2018/06

 Times Cited Count:10 Percentile:45.99(Physics, Applied)

The advantage of SiO$$_{2}$$/AlON stacked gate dielectrics over SiO$$_{2}$$, AlON and Al$$_{2}$$O$$_{3}$$ single dielectric layers was demonstrated. Our systematic research revealed that the optimized stacked structure with 3.3-nm-thick AlON interlayer is beneficial in terms of superior interface quality, reduced gate leakage current and C-V hysteresis for next-generation high frequency and high power AlGaN/GaN MOS-HFETs.

Oral presentation

Influence of deposition power and temperature on SiO$$_{2}$$/AlGaN interface property deposited by PECVD

Terashima, Daiki*; Watanabe, Kenta*; Yamada, Takahiro*; Nozaki, Mikito*; Shih, H.*; Nakazawa, Satoshi*; Anda, Yoshiharu*; Ueda, Tetsuzo*; Yoshigoe, Akitaka; Hosoi, Takuji*; et al.

no journal, , 

Impact of input power and substrate temperature of SiO$$_{2}$$ deposition by plasma-enhanced CVD on SiO$$_{2}$$/AlGaN interface was investigated by means of electrical characterization of MOS capacitors. Synchrotron radiation photoemission spectroscopy revealed that Ga oxide component on AlGaN surface increases with increasing input power of PECVD. MOS capacitors with SiO$$_{2}$$ gate insulator deposited at low input power shows relatively better SiO$$_{2}$$/AlGaN interface quality, despite degraded interface quality for the sample with SiO$$_{2}$$ deposited at high input power. These results suggest that AlGaN surface oxidation during oxide deposition should be controlled to obtain good interface property.

Oral presentation

SiO$$_{2}$$/AlON stacked gate dielectrics for AlGaN/GaN MOS-HFET

Watanabe, Kenta*; Terashima, Daiki*; Nozaki, Mikito*; Yamada, Takahiro*; Nakazawa, Satoshi*; Ishida, Masahiro*; Anda, Yoshiharu*; Ueda, Tetsuzo*; Yoshigoe, Akitaka; Hosoi, Takuji*; et al.

no journal, , 

The advantage of SiO$$_{2}$$/AlON stacked gate dielectrics over SiO$$_{2}$$, AlON and Al$$_{2}$$O$$_{3}$$ single dielectric layers was demonstrated. Our systematic research revealed that the optimized stacked structure with 3.3-nm-thick AlON interlayer is beneficial in terms of superior interface quality, reduced gate leakage current and C-V hysteresis for next-generation high frequency and high power AlGaN/GaN MOS-HFETs.

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