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Report No.

Interface engineering of Ge MOS devices with Zr0$$_{2}$$ gate dielectrics

Hosoi, Takuji*; Okamoto, Gaku*; Kutsuki, Katsuhiro*; Kagei, Yusuke*; Harries, J.; Yoshigoe, Akitaka ; Teraoka, Yuden; Shimura, Takayoshi*; Watanabe, Heiji*

We developed high quality high-$$k$$/Ge gate stacks with reduced leakage current and superior interface quality, which was fabricated by direct deposition of ZrO$$_{2}$$ on Ge substrate and thermal oxidation. Synchrotron radiation photoelectron spectroscopy revealed that thermal oxidation at 823 K caused not only an intermixing between ZrO$$_{2}$$ and Ge but also the formation of GeO$$_{2}$$ at the interlayer. We obtained an equivalent oxide thickness (EOT) of 1.9 nm, and an interface state density of 10$$^{11}$$ cm$$^{-2}$$eV$$^{-1}$$ for Au/ZrO$$_{2}$$/Ge capacitors. Furthermore, we found that the A1$$_{2}$$0$$_{3}$$ capping on the Zr0$$_{2}$$ 1ayer is effective for decreasing EOT. The interface state density as low as 5.3$$times$$10$$^{10}$$ cm$$^{-2}$$eV$$^{-1}$$ was obtained for the Al$$_{2}$$O$$_{3}$$/ZrO$$_{2}$$/Ge stack with 30 min oxidation. The EOT could be reduced to l.6 nm by 10 min oxidation. The leakage current was two orders of magnitude lower than the conventional poly-Si/SiO$$_{2}$$/Si stack.



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