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Zr0$$_{2}$$ゲー卜絶縁膜を用いたGe MOSデバイスの界面設計

Interface engineering of Ge MOS devices with Zr0$$_{2}$$ gate dielectrics

細井 卓治*; 岡本 学*; 朽木 克博*; 景井 悠介*; Harries, J.; 吉越 章隆 ; 寺岡 有殿; 志村 考功*; 渡部 平司*

Hosoi, Takuji*; Okamoto, Gaku*; Kutsuki, Katsuhiro*; Kagei, Yusuke*; Harries, J.; Yoshigoe, Akitaka; Teraoka, Yuden; Shimura, Takayoshi*; Watanabe, Heiji*

われわれはリーク電流を減少させて優れた界面特性を持った高品質のhigh-$$k$$/Geゲートスタックを開発した。この製作にはGe基板上への直接ZrO$$_{2}$$デポジションとその加熱酸化が行われた。放射光光電子分光によると、ZrO$$_{2}$$/Ge構造の823Kでの熱酸化はZrO$$_{2}$$とGeの相互拡散がかりでなく、GeO$$_{2}$$界面層の生成をもたらした。等価酸化膜厚(EOT)は1.9nmで、界面準位密度はAu/ZrO$$_{2}$$/Geキャパシタで10$$^{11}$$cm$$^{-2}$$eV$$^{-1}$$と小さかった。さらに、Zr0$$_{2}$$層上にA1$$_{2}$$0$$_{3}$$を形成するとさらにEOTを小さくできることを見いだした。界面準位密度はAl$$_{2}$$O$$_{3}$$/ZrO$$_{2}$$/Geの30分の加熱で5.3$$times$$10$$^{10}$$cm$$^{-2}$$eV$$^{-1}$$であった。10分加熱では1.6nmまでEOTを低減できた。その場合のリーク電流は従来のpoly-Si/SiO$$_{2}$$/Siスタックに比べて二桁低い。

We developed high quality high-$$k$$/Ge gate stacks with reduced leakage current and superior interface quality, which was fabricated by direct deposition of ZrO$$_{2}$$ on Ge substrate and thermal oxidation. Synchrotron radiation photoelectron spectroscopy revealed that thermal oxidation at 823 K caused not only an intermixing between ZrO$$_{2}$$ and Ge but also the formation of GeO$$_{2}$$ at the interlayer. We obtained an equivalent oxide thickness (EOT) of 1.9 nm, and an interface state density of 10$$^{11}$$ cm$$^{-2}$$eV$$^{-1}$$ for Au/ZrO$$_{2}$$/Ge capacitors. Furthermore, we found that the A1$$_{2}$$0$$_{3}$$ capping on the Zr0$$_{2}$$ 1ayer is effective for decreasing EOT. The interface state density as low as 5.3$$times$$10$$^{10}$$ cm$$^{-2}$$eV$$^{-1}$$ was obtained for the Al$$_{2}$$O$$_{3}$$/ZrO$$_{2}$$/Ge stack with 30 min oxidation. The EOT could be reduced to l.6 nm by 10 min oxidation. The leakage current was two orders of magnitude lower than the conventional poly-Si/SiO$$_{2}$$/Si stack.

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