Verification of soft-error rate estimation method in a logic LSI

Makino, Takahiro; Onoda, Shinobu; Hirao, Toshio; Oshima, Takeshi; Kobayashi, Daisuke*; Hirose, Kazuyuki*

We want to reveal the relation between SET-induced soft-error rates (s) and SET pulse-width distribution to be able to reduce the with an SET filter like an RC filter or a temporal latch architecture. By considering the relation between and SET pulse-width, we can determine the minimum time constant for the SET filter to reduce the effectively. A theoretical estimation has been proposed to obtain in a logic LSI from SET pulse-widths measured in logic cells and the latch probability of SET pulses at flip-flops (FFs) used in logic LSIs. However, the estimation method has not been verified yet. In this paper, we verify the theoretical estimation method.