Refine your search:     
Report No.

Interface engineering of ZrO$$_{2}$$/Ge gate stacks by post-deposition annealing and Al$$_{2}$$O$$_{3}$$ capping layers

Watanabe, Heiji*; Okamoto, Gaku*; Kutsuki, Katsuhiro*; Harries, J.; Yoshigoe, Akitaka ; Teraoka, Yuden; Hosoi, Takuji*; Shimura, Takayoshi*

We fabricated high-quality high-k/Ge gate stacks by direct deposition of ZrO$$_{2}$$ layers on Ge substrates and subsequent post-deposition annealing. Synchrotron-radiation X-ray photoelectron spectroscopy revealed that thermally oxidizing a ZrO$$_{2}$$/Ge structure at 823 K caused not only ZrO$$_{2}$$ and Ge to intermix but also a pure GeO$$_{2}$$ interlayer to form. By optimizing subsequent oxidation conditions, we obtained a minimum EOT of 1.9 nm, negligible C-V hysteresis, and an interface state density (Dit) of a few 10$$^{11}$$ cm$$^{-2}$$eV$$^{-1}$$ for Au/ZrO$$_{2}$$/Ge capacitors. We also developed Al$$_{2}$$O$$_{3}$$/ZrO$$_{2}$$ stacked gate dielectrics to control interface reaction during the post treatment. The Al$$_{2}$$O$$_{3}$$ capping on the ZrO$$_{2}$$ layer was found to be beneficial for further EOT scaling because it suppressed excess interface reaction. Scaled EOT value down to 1.6 nm and leakage current reduction were achieved.



- Accesses





[CLARIVATE ANALYTICS], [WEB OF SCIENCE], [HIGHLY CITED PAPER & CUP LOGO] and [HOT PAPER & FIRE LOGO] are trademarks of Clarivate Analytics, and/or its affiliated company or companies, and used herein by permission and/or license.