Interface engineering of ZrO/Ge gate stacks by post-deposition annealing and AlO capping layers

Watanabe, Heiji*; Okamoto, Gaku*; Kutsuki, Katsuhiro*; Harries, J.; Yoshigoe, Akitaka ; Teraoka, Yuden; Hosoi, Takuji*; Shimura, Takayoshi*

We fabricated high-quality high-k/Ge gate stacks by direct deposition of ZrO layers on Ge substrates and subsequent post-deposition annealing. Synchrotron-radiation X-ray photoelectron spectroscopy revealed that thermally oxidizing a ZrO/Ge structure at 823 K caused not only ZrO and Ge to intermix but also a pure GeO interlayer to form. By optimizing subsequent oxidation conditions, we obtained a minimum EOT of 1.9 nm, negligible C-V hysteresis, and an interface state density (Dit) of a few 10 cmeV for Au/ZrO/Ge capacitors. We also developed AlO/ZrO stacked gate dielectrics to control interface reaction during the post treatment. The AlO capping on the ZrO layer was found to be beneficial for further EOT scaling because it suppressed excess interface reaction. Scaled EOT value down to 1.6 nm and leakage current reduction were achieved.