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FPGA utilization of the accelerator interlock system through MPS development in LIPAc

Nishiyama, Koichi; Takahashi, Hiroki ; Sakaki, Hironao; Narita, Takahiro; Kojima, Toshiyuki*; Knaster, J.*; Marqueta, A.*

The development of IFMIF(International Fusion Material Irradiation Facility) to generate a 14 MeV source of neutrons with the spectrum of DT fusion reactions is indispensable to qualify suitable materials for the First Wall of the nuclear vessel in fusion power plants. As part of IFMIF validation activities, LIPAc (Linear IFMIF Prototype Accelerator) facility, currently under installation at Rokkasho (Japan), will accelerate a 125 mA CW and 9 MeV deuteron beam with a total beam power of 1.125 MW. The Machine Protection System (MPS) of LIPAc provides an essential interlock function of stopping the beam in case of anomalous beam loss or other hazardous situations. High speed processing is necessary to achieve properly the MPS main goal. This high speed processing of the signals, distributed alongside the accelerator facility, is based on FPGA (Field Programmable Gate Array) technology. This paper describes the basis of FPGA use in the accelerator interlock system through the development of LIPAc.

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