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論文

Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

Irmler, C.*; 谷田 聖; 他98名*

Journal of Instrumentation (Internet), 11(1), p.C01087_1 - C01087_9, 2016/01

 被引用回数:5 パーセンタイル:34.01(Instruments & Instrumentation)

The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests.

論文

EMC studies for the vertex detector of the Belle II experiment

Thalmeier, R.*; 谷田 聖; 他102名*

Journal of Instrumentation (Internet), 11(1), p.C01044_1 - C01044_10, 2016/01

 被引用回数:2 パーセンタイル:14.5(Instruments & Instrumentation)

The upgrade of the Belle II experiment plans to use a vertex detector based on two different technologies, DEPFET pixel (PXD) technology and double side silicon microstrip (SVD) technology. The vertex electronics are characterized by the topology of SVD bias that forces to design a sophisticated grounding because of the floating power scheme. The complex topology of the PXD power cable bundle may introduce some noise inside the vertex area. This paper presents a general overview of the EMC issues present in the vertex system, based on EMC tests on an SVD prototype and a study of noise propagation in the PXD cable bundle based on Multi-conductor transmission line theory.

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