細井 卓治*; 桐野 嵩史*; 上西 悠介*; 池口 大輔*; Chanthaphan, A.*; 吉越 章隆; 寺岡 有殿; 箕谷 周平*; 中野 佑紀*; 中村 孝*; et al.
Workshop digest of 2012 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD 2012), p.22 - 25, 2012/06
SiC is a promising material for high-power electronic devices. Although SiO film can be grown on SiC by thermal oxidation, low channel mobility and poor gate oxide reliability are the critical issues for SiC power MOSFETs. In this work, we investigated the fundamental aspects of thermally-grown SiO/4H-SiC structures such as an energy band alighnment and flatband voltage instability. Both electrical characterization and XPS study revealed that a conduction band offset between SiO and SiC is extrinsically increased. High temperature annealing in H could passivate mobile ions existing in as-oxidized SiO/SiC structures. Post-oxidation annealing in Ar eliminates the mobile ions, but they are generated again by subsequent high-temperature hydrogen annealing. These features were not observed for SiO/Si structures, and thus considered to be inherent to thermally grown SiO/SiC structures.
渡部 平司*; 細井 卓治*; 桐野 嵩史*; 上西 悠介*; Chanthaphan, A.*; 吉越 章隆; 寺岡 有殿; 箕谷 周平*; 中野 佑紀*; 中村 孝*; et al.
Materials Science Forum, 717-720, p.697 - 702, 2012/05
We investigated the interface between oxide and 4H-SiC(0001) Si-face or (000-1) C-face by synchrotron radiation photoelectron spectroscopy. The Si 2p spectra were fitted with bulk SiC and SiO together with intermediate oxides (Si, Si, Si). The total amount of intermediate states was sufficiently small compared with that of the remaining oxides. This implies that the transition layer in the oxide is as thin as a few atomic layers. Moreover, the chemical composition in the bulk region was found to be almost identical to that of the initial SiC surface. These results indicate formation of a near-perfect SiO/SiC interface.
細井 卓治*; 桐野 嵩史*; Chanthaphan, A.*; 上西 悠介*; 池口 大輔*; 吉越 章隆; 寺岡 有殿; 箕谷 周平*; 中野 佑紀*; 中村 孝*; et al.
Materials Science Forum, 717-720, p.721 - 724, 2012/05
The energy band alignments of thermally grown SiO/SiC structures were investigated by means of synchrotron radiation photoelectron spectroscopy (SR-PES) and electrical characterization of SiC-MOS capacitors. In order to determine the energy band alignments of SiO/SiC, band gaps of the thermal oxides and valence band offsets at the interface were examined by SR-PES. SiC-MOS capacitors with Al electrodes were also fabricated to evaluate interface state density and conduction band offset. Experimental results indicate that hydrogen atoms are effective to terminate carbon-related defects. It can be concluded that interface quality degradation due to hydrogen desorption by vacuum annealing causes reduction of conduction band offset for thermally grown SiO/SiC structure.
渡部 平司*; 細井 卓治*; 桐野 嵩史*; 景井 悠介*; 上西 悠介*; Chanthaphan, A.*; 吉越 章隆; 寺岡 有殿; 志村 考功*
Applied Physics Letters, 99(2), p.021907_1 - 021907_3, 2011/07
The correlation between atomic structure and the electrical properties of thermally grown SiO/4H-SiC(0001) interfaces was investigated by synchrotron X-ray photoelectron spectroscopy together with electrical measurements of SiC-MOS capacitors. We found that the oxide interface was dominated by Si-O bonds and that there existed no distinct C-rich layer beneath the SiC substrate despite literature. In contrast, intermediate oxide states in Si core-level spectra attributable to atomic scale roughness and imperfection just at the oxide interface increased as thermal oxidation progressed. Electrical characterization of corresponding SiC-MOS capacitors also indicated an accumulation of both negative fixed charges and interface defects, which correlates well with the structural change in the oxide interface and provides insight into the electrical degradation of thermally grown SiC-MOS devices.
渡部 平司*; 桐野 嵩史*; 上西 悠介*; Chanthaphan, A.*; 吉越 章隆; 寺岡 有殿; 箕谷 周平*; 中野 佑紀*; 中村 孝*; 細井 卓治*; et al.
ECS Transactions, 35(2), p.265 - 274, 2011/05
The use of AlON gate insulator for SiC-based MOS power devices is proposed. Although direct deposition of AlON on 4H-SiC substrate causes electrical degradation, the fabricated MOS capacitor with AlON/SiO stacked gate dielectric shows no flatband voltage shift and negligible capacitance-voltage (C-V) hysteresis. Owing to the high dielectric constant of AlON, significant gate leakage reduction was achieved even at high temperatures. Moreover, in order to improve electrical properties of thermally grown SiO/SiC interfaces, the impact of a combination treatment of nitrogen plasma exposure and forming gas annealing was investigated. Channel mobility enhancement of SiC-MOSFETs was consistent with the reduction in interface state density depending on the process conditions of the combination treatment, and obtained 50% mobility enhancement, while maintaining low gate leakage current.
渡部 平司*; 細井 卓治*; 桐野 嵩史*; 上西 悠介*; Chanthaphan, A.*; 池口 大輔*; 吉越 章隆; 寺岡 有殿; 箕谷 周平*; 中野 佑紀*; et al.
ECS Transactions, 41(3), p.77 - 90, 2011/00
It is well known that SiC-based MOS devices have suffered from degraded electrical properties of thermally grown SiO/SiC interfaces, such as low inversion carrier mobility and deteriorated gate oxide reliability. This paper overviews the fundamental aspects of SiC-MOS devices and indicates intrinsic obstacles connected with an accumulation of both negative fixed charges and interface defects and with a small conduction band offset of the SiO/SiC interface which leading to the increased gate leakage current of MOS devices. To overcome these problems, we proposed using aluminum oxynitride insulators stacked on thin SiO underlayers for SiC-MOS devices. Superior flatband voltage stability of AlON/SiO/SiC gate stacks was achieved by optimizing the thickness of the underlayer and nitrogen concentration in the high-k dielectrics. Moreover, we demonstrated reduced gate leakage current and improved current drivability of SiC-MOSFETs with AlON/SiO gate stacks.
朽木 克博*; 岡本 学*; 秀島 伊織*; 上西 悠介*; 桐野 嵩史*; Harries, J.; 吉越 章隆; 寺岡 有殿; 細井 卓治*; 志村 考功*; et al.
no journal, ,
高性能Geデバイスの実現には、高誘電率絶縁膜形成とその界面制御技術の確立が必須である。ZrO薄膜をGe基板上に堆積し、その後熱酸化処理を施したスタックは、優れたMOS界面特性を示す一方で、GeO界面層が形成されることにより等価SiO換算膜厚(EOT: Equivalent Oxide Thickness)が2nm以上となってしまう。本研究では、高密度プラズマ窒化により形成したGeN膜の優れた熱的安定性・耐酸化性に注目し、ZrO/Ge3N/Ge構造を作製し、熱処理後の界面構造について大型放射光施設SPring-8のBL23SUを用いて光電子分光法により評価した。Ge3d及びN1s内殻準位スペクトルの高分解能測定から、823Kの熱酸化処理によって界面GeN層はわずかに酸化するものの安定に存在することを確認し、また1.8nmのEOTを実現した。