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Gate stack technologies for SiC power MOSFETs

SiCを用いた電力用MOSFET向けのゲートスタック技術

渡部 平司*; 細井 卓治*; 桐野 嵩史*; 上西 悠介*; Chanthaphan, A.*; 池口 大輔*; 吉越 章隆 ; 寺岡 有殿; 箕谷 周平*; 中野 佑紀*; 中村 孝*; 志村 考功*

Watanabe, Heiji*; Hosoi, Takuji*; Kirino, Takashi*; Uenishi, Yusuke*; Chanthaphan, A.*; Ikeguchi, Daisuke*; Yoshigoe, Akitaka; Teraoka, Yuden; Mitani, Shuhei*; Nakano, Yuki*; Nakamura, Takashi*; Shimura, Takayoshi*

It is well known that SiC-based MOS devices have suffered from degraded electrical properties of thermally grown SiO$$_{2}$$/SiC interfaces, such as low inversion carrier mobility and deteriorated gate oxide reliability. This paper overviews the fundamental aspects of SiC-MOS devices and indicates intrinsic obstacles connected with an accumulation of both negative fixed charges and interface defects and with a small conduction band offset of the SiO$$_{2}$$/SiC interface which leading to the increased gate leakage current of MOS devices. To overcome these problems, we proposed using aluminum oxynitride insulators stacked on thin SiO$$_{2}$$ underlayers for SiC-MOS devices. Superior flatband voltage stability of AlON/SiO$$_{2}$$/SiC gate stacks was achieved by optimizing the thickness of the underlayer and nitrogen concentration in the high-k dielectrics. Moreover, we demonstrated reduced gate leakage current and improved current drivability of SiC-MOSFETs with AlON/SiO$$_{2}$$ gate stacks.

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