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Impact of stacked AlON/SiO$$_{2}$$ gate dielectrics for SiC power devices

SiCパワーデバイスのための積層AlON/SiO$$_{2}$$ゲート絶縁膜開発

渡部 平司*; 桐野 嵩史*; 上西 悠介*; Chanthaphan, A.*; 吉越 章隆 ; 寺岡 有殿; 箕谷 周平*; 中野 佑紀*; 中村 孝*; 細井 卓治*; 志村 考功*

Watanabe, Heiji*; Kirino, Takashi*; Uenishi, Yusuke*; Chanthaphan, A.*; Yoshigoe, Akitaka; Teraoka, Yuden; Mitani, Shuhei*; Nakano, Yuki*; Nakamura, Takashi*; Hosoi, Takuji*; Shimura, Takayoshi*

The use of AlON gate insulator for SiC-based MOS power devices is proposed. Although direct deposition of AlON on 4H-SiC substrate causes electrical degradation, the fabricated MOS capacitor with AlON/SiO$$_{2}$$ stacked gate dielectric shows no flatband voltage shift and negligible capacitance-voltage (C-V) hysteresis. Owing to the high dielectric constant of AlON, significant gate leakage reduction was achieved even at high temperatures. Moreover, in order to improve electrical properties of thermally grown SiO$$_{2}$$/SiC interfaces, the impact of a combination treatment of nitrogen plasma exposure and forming gas annealing was investigated. Channel mobility enhancement of SiC-MOSFETs was consistent with the reduction in interface state density depending on the process conditions of the combination treatment, and obtained 50% mobility enhancement, while maintaining low gate leakage current.

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